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In cases like these I typically use generate statements in my verilog so that I can control what gets synthesized.... not sure if VHDL has a similar feature though
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Annie get your gun?
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The only way I can think of preventing those messages without using the attributes is to have your HDL generated on the fly using a generation callback.
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I found an example of this 'generation call-back' in a thread by
dwh@ovro.caltech.edu(
http://www.alteraforum.com/forum/showthread.php?t=26957 (
http://www.alteraforum.com/forum/showthread.php?t=26957)). This looks feasible to me. As I have to write a wrapper around my 'subset' to get the proper ST-names anyway, I might as well generate the port list and connect it up.
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As for a lack of generics, I'm not sure about that one since I was under the impression they were supported so this is news to me
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If you take a look at e.g. the ST-splitter code you will see that all the 16 (which is the maximum supported according to the user guide) ports are defined (the code is in SystemVerilog) and the 'elaborate' call-back does some work on the unused. There is no 'generation' call-back.
The approach taken can be called 'using generics' if you do the extra work of either writing the fully expanded ports list and 'elaborate' what is actually used or 'generate' a new file. True generics would result in using std_logic_2D for the data and std_logic_vectors for the signals, like:
NUMBER_OF_SINKS : positive := 32 ;
...
asi_data : out std_logic_2D(NUMBER_OF_SINKS -1 downto 0, WIDTH_D - 1 downto 0) ;
asi_ready : out std_logic_vector( NUMBER_OF_SINKS -1 downto 0) ;
....
Excuse me for the VHDL, I don't know enough of Verilog to type it out just on top of my head :)
The std_logic_2D is defined in the LPM library and matches the AHDL double array: a[][] construct.
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