How to design a component which has N number of Avalon ST Sink ports in SOPC Builder

Stubbed outputs will remain stubbed in the hardware so the usual synthesis optimizations will apply to those and you'll get the appropriate messages from Quartus II about it. Typically I tag my HDL with attributes to prevent those Quartus messages from occurring. In cases like these I typically use generate statements in my verilog so that I can control what gets synthesized.... not sure if VHDL has a similar feature though. The only way I can think of preventing those messages without using the attributes is to have your HDL generated on the fly using a generation callback.

I'm not a .tcl expert but I have found tweaking .tcl files after they are generated by component editor to be fairly trivial. I also don't think there is a cleaner solution to this problem since this is the price you pay for implementing/using highly parameterizable IP. The tools can't magically implement the interfaces for you since at the end of the day those interfaces connect to your own logic so I don't really see what you are getting at....

As for a lack of generics, I'm not sure about that one since I was under the impression they were supported so this is news to me. I know historically generics have been problematic but I don't think they were completely omitted from the product support.