How to design a component which has N number of Avalon ST Sink ports in SOPC Builder

Could be an academic question perhaps, what do yo do if you would want to allow up to (let's say) 512 Sinks in a single component?

The suggested (and used by Altera) method to just enumerate a number of ST interfaces, and them 'stubbing' them out at instantiation time can be 'at best' called clumsy. It also will probably generate another zilllion warnings during Analysis, just cluttering up the Message-Window?

I devised my own Source-Sink protocol before Avalon-ST came into play. It can be easily mapped into a subset of the ST-signals, and I'm going to migrate this into QSys/SoPC but the missing generics make me wonder.

I just checked the .sv and .tcl of the ST-splitter. I wonder if it will be easier in VHDL?