Honored Contributor
Honored ContributorThanks for the time invested in explaining all this to me. I understand overall what you have explained but this has also created new queries because I could not succeed in implementing your suggestions. So to start, let's break it down again:
--- Quote Start --- Yes, you can have 2 32-bit PIOs. --- Quote End --- OK, I managed to do that based on another forum post . --- Quote Start --- Before getting into this, you should ask the question "do you NEED to?" --- Quote End --- Yes, I need to make it work on FPGA using its parallelism resources. I understand your reasons for not using it this way, but my task is more educational than real-world. I am just stepping into FPGA world and this is my way to learn. --- Quote Start --- But to utilize the FPGA resources and gain serious speedup, you would add a wrapper module that replicates the Sobel module. The Nios in this case would probably be doing some DMA transfer or providing the Avalon-MM address to a memory location --- Quote End --- My other attempt was to discard the PIOs and instead create an SOPC component with Avalon-MM. But I don't know how to create a wrapper module to instantiate more Sobel submodules. I've downloaded the Avalon Memory-Mapped Slave Template from Altera website, inserted as a component in SOPC and renamed as my_slave_component. However, I don't know what to put as the Register File properties (Word Size and Synchronization) and capabilities (I have enabled only two registers - one input and one output. Is that good?). When I looked at the my_slave_component.v to modify it and add my custom logic to it, I saw many new input/output ports.
input wire clk, // clock_reset.clk
input wire reset, // clock_reset_reset.reset
input wire slave_address, // s0.address
input wire slave_read, // .read
input wire slave_write, // .write
output wire slave_readdata, // .readdata
input wire slave_writedata, // .writedata
input wire slave_byteenable, // .byteenable
output wire user_dataout_0, // user_interface.export
input wire user_datain_1
