How to call tightly couple module during C code for NIOS II

Thank you gaudetteje for the sample code. Looking at your code, I realized I made a mistake with the direction of the inpt/ouput ports. But I am still facing problems compiling. So let's start fault finding.

- I have 3 PIOs in SOPC Builder. 2 out (data_out_0 and data_out_1) and 1 in (result_in0)

- Then in my main.v file port declaration, I put

input result_data;
output int_data_line0;
output int_data_line1;

- In the SOPC generated NIOS system, I put

nios_system NiosII (
// my pios
 .in_port_to_the_result_in0    (result_data),
  .out_port_from_the_data_out0  (int_data_line0),
  .out_port_from_the_data_out1  (int_data_line1),
);

-Finally I instantiate my custom verilog module

add_two two_vals(
      .clk(system_clock),
     .line_1_in (int_data_line0),
     .line_2_in (int_data_line1),
     .result_back_out(result_data),
     );

When I compile this, I get Error : Net "result_data",which fans out to "nios_system:NiosII|in_port_to_the_result_in0[0]", cannot be assigned to more than one value.

Could this error be due to a badly written add_two.v module? I still have the module as before except I add tried to add a clock to it :

module add_two (
// Inputs
clk,
line_1_in,
line_2_in,
// Output
result_back_out
);
 
//Port Declarations
// Inputs
input clk;
input   line_1_in; // 8 bit value 
input   line_2_in;
// Output
output wire  result_back_out; // assume 8 bit
 
reg  original_line_1;
reg  original_line_2;
reg   temp_sum;
 
always@ (posedge clk)
 begin 
  original_line_1 <= line_1_in;
  original_line_2 <= line_2_in;
  temp_sum <= original_line_1 + original_line_2;
 end
assign result_back_out = temp_sum ;
endmodule

I also saw a warning message in SOPC builder for that PIO In when I generated the system which said: 'PIO Inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.'. Am I doing something wrong there too?