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Altera_Forum
Honored Contributor
14 years agoHere's an example, as promised.
In my top level .v file, I have the following:// Instantiate Nios II/e CPU
cpu_accel CPU0 (
.clk_0(CLOCK_CPU),
.in_port_to_the_data_in0(int_datain),
.out_port_from_the_data_out0(int_dataout0),
.out_port_from_the_data_out1(int_dataout1),
.reset_n(KEY),
);
// Instantiate custom accelerated verilog component
FIR FIR0 (
.PIO_in0(int_dataout0),
.PIO_in1(int_dataout1),
.PIO_out0(int_datain0)
);"cpu_accel.v" is my generated SOPC builder system. "FIR" is my custom Verilog module. 'int_datain' and 'int_dataout' are simply defined as wires. You can use IO_RD and IO_WR. In this case, I simply used pointers:
<snip>
int main(int argc, char* argv) {
// PIO pointers
int* data_out0 = (int *) DATA_OUT0_BASE;
int* data_out1 = (int *) DATA_OUT1_BASE;
volatile int* data_in0 = (int *) DATA_IN0_BASE;
int res;
<snip>
*(data_out1) = 1;
*(data_out0) = 2;
// insert wait statement here, if necessary
res = *data_in0; // copy result to local int
<snip>