Forum Discussion
Altera_Forum
Honored Contributor
10 years agoAs with many things, there is no one answer here. It depends on number of factors and design decisions. Vectored interrupts or standard exception funnel? All ISRs in exception memory? etc, etc.
Initially, I would start with one of the design examples and see how it works for you. Since this is an FPGA, nothing is set in stone and you can adjust it as you learn how which options you choose affect the .exception size. Good luck! slacker