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Altera_Forum
Honored Contributor
21 years agoHi,
We put some more detail on this in Chapter 17 of the Nios II Processor Reference Handbook. See Multiply & Divide Performance on p. 17-4, and see Table 17-2 on p. 17-5. The multiply performance depends on the FPGA target and the CPU implementation. The hardware divide performance is unaffected by the existance of DSP blocks. Kerry Altera