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Altera_Forum
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15 years ago

How do Nios-II handle IP address change during the TCP/IP connection?

Dear all,

I have problem with changing IP address in the FPGA board.

Here is my case, let say I have a FPGA board which is connected to PC. The PC sends a command to the FPGA that asks the FPGA to change its IP address to a new given IP address.

Here is my idea to handle this task :

  1. After receiving IP changes command from PC, both FPGA and PC terminate their TCP/IP connection by close their socket.

  2. The FPGA does the IP changes mechanism

  3. Both FPGA and PC initiate a new TCP/IP connection like usual

  4. The FPGA sends acknowledgement to the PC to tell that it already changes its IP address successfully.

Up to here, what do you think guys? Is my idea correct? :confused:

Now I'm facing problem with step no.2 above. To change the FPGA's IP address, what I'm thinking is in the FPGA I have to do these steps :

  1. Terminate the previous TCP/IP connection (close the exist socket)

  2. Assign new IP address to the FPGA (I have made a new function called 'change_ip' which is basically same as get_ip_addr function provided by altera)

  3. Initiate new TCP/IP connection (create, bind, listen socket)

But the result is error, I got this following error message :

: See STDERR for expanded diagnosis translation.
:  Bind failed
:  ERRNO: : 
: See STDERR (FAULT_LEVEL is SYSTEM).
: FAULT_LEVEL is SYSTEM.
: FATAL Error, Restart required.
: Locking scheduler - endless loop.

I also tried to kill the previous "inet main" and "clock tick" tasks, but in the end it also ends up with the same error message.

Anybody know how is the correct procedure to change FPGA's IP address? :confused: :confused:

Thanks for any comments or suggestions!

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