Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHello,
You can add an Sram component to your qsys configuration, connect it with the Nios II processor, compile it. Then go to quartus, instantiate the verilog/VHDL object generated by qsys in quartus, connect the i/o and that should do it. Altera has tuturials that cover the first step in the altera university forum. Best Regards, Johi