--- Quote Start ---
Hi Alex,
Sorry for the delay in responding. It looks like you may be having a problem with cache coherency. Please check the follow items in your system:
- The SMP bit in the ACTLR register in the ARM core must be set before enabling the MMU. This should be done by the OS, but it is good to check.
- The SCU must be on.
- The memory space should be marked as shared and the secure bit must be set the same for the FPGA master and the HPS.
- The cache properties must be the same for the FPGA master and the HPS and you should use write allocate for the cache.
- The ARUSER and AWUSER bits in the ACP ID Mapper registers should be set to 5'b11111.
Please let me know if these suggestions solve your problem. If not, we'll look further.
Regards,
Sue
--- Quote End ---
Hi Scozart,
I also have the same question for the thread. I am using the SoCKit board with Linux. I write an AXI master in System Verilog. This master is integrated into Qsys and connected to the FPGA-to-HPS bridge. In my test, this AXI master can access FPGA-RAM. However, It can't access HPS-RAM. In this situation, the written address of this AXI master is the virtual address obtained by malloc() in Linux. The ARUSER and AWUSER pins of this AXI master are set to 5'b11111. The AWCACHE and ARCACHE pins of this AXI master are set to 4'b1111. I write a program in Linux to check whether the data at the virtual address is the same as the written data of this AXI master. The result is that the data at the virtual address in Linux is not changed.
Thank for your attention.
--AJMachine
Honored Contributor
