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Altera_Forum
Honored Contributor
Honored ContributorHow can I get data from FPGA frabic via FPGA-to-HPS?
Hello, I implement the a soft-IP AXI master in FPGA and transmit the data to HPS side via FPGA2HPS bridge, I set ACP-port as "dynamic" mode. BUT how can I read the data via DS-5 program registe...
Altera_ForumHonored Contributor
Honored ContributorHi Alex,
Sorry for the delay in responding. It looks like you may be having a problem with cache coherency. Please check the follow items in your system:- The SMP bit in the ACTLR register in the ARM core must be set before enabling the MMU. This should be done by the OS, but it is good to check.
- The SCU must be on.
- The memory space should be marked as shared and the secure bit must be set the same for the FPGA master and the HPS.
- The cache properties must be the same for the FPGA master and the HPS and you should use write allocate for the cache.
- The ARUSER and AWUSER bits in the ACP ID Mapper registers should be set to 5'b11111.
