how can i access the output

If your custom core is accessed rapidly with multiple inputs (and as a result it returns multiple outputs) I don't recommend having software in the critical path. For example if I had some hardware that simply sums all the inputs I write to it and it provides me the running sum as the inputs are arriving I would have one slave port I write the inputs to and a second slave port I read the results from. Results would be written into a buffer (FIFO) so that I could iscolate the input and output and access the component faster. This would also be the most appropriate approach if you used a DMA engine to move data to/from the hardware which is much more efficient than having a processor moving bulk data.

Having the processor twiddling it's thumbs for 26 cycles per input is not very efficient so having a FIFO iscolate the input and the output so that the processor can perform other tasks in between is a more efficient use of those processor cycles. If you don't care about this inefficiency then just implement you component to either issue a wait request when you go to read the result, or just include the read data valid signal so that it can return the valid data any time after the CPU issues the read.