How calculate tSU, tH, and tCO from rise & fall of TIMEQUEST Report datasheet

I'm trying to use SDRAM Controller, the SDRAM CLK need to be shifted (such as -60 degrees), so I have to caculate the phase(ns) between CPU clock and SDRAM clock.

According to the "Embedded Peripherals IP User Guide 2016.06.17" page 2-13, the flowing five values are very important.

Clock period tCLK

Minimum clock-to-output time tCO_MIN

Maximum clock-to-output time tCO_MAX

Maximum hold time after clock tH_MAX

Maximum setup time before clock tSU_MAX

I have went every corner of TIMEQUEST GUI, I can't find any thing that can get me the direct answer to clock-to-output time, hold time after clock and setup time before clock.

My QSYS design has a 100Mhz clock, and I know the tCLK should be 10ns. The report datasheet should contain the time values that I want, but I don't know how to convert these rise/fall into tSU, tH, and tCO?

CLKIN_50M

->PLL.c[0] 100Mhz nios2 SDRAM Control

->PLL.c[1] 24Mhz

->PLL.c[2] 100Mhz SDRAM CLK with phase shift(-60deg)

Setup Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
SDRAM_DQ
    CLKIN_50M    3.776    3.951    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.754    3.929    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.766    3.941    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.766    3.941    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.740    3.915    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.724    3.899    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.766    3.941    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.776    3.951    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.759    3.934    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.739    3.914    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.754    3.929    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.744    3.919    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.736    3.911    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.760    3.935    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.753    3.928    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.726    3.901    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.746    3.921    Rise    u1|altpll_component|auto_generated|pll1|clk

Hold Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
SDRAM_DQ
    CLKIN_50M    -3.122    -3.297    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.153    -3.328    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.165    -3.340    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.165    -3.340    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.139    -3.314    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.122    -3.297    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.165    -3.340    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.175    -3.350    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.158    -3.333    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.138    -3.313    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.152    -3.327    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.142    -3.317    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.135    -3.310    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.159    -3.334    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.152    -3.327    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.125    -3.300    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.145    -3.320    Rise    u1|altpll_component|auto_generated|pll1|clk

Clock to Output Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
CORE_CLK    CLKIN_50M    0.900        Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A
    CLKIN_50M    0.823    0.796    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.818    0.791    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.818    0.791    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.823    0.796    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.813    0.786    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.808    0.781    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.798    0.771    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.806    0.779    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.788    0.761    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.789    0.762    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.778    0.751    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.799    0.772    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.799    0.772    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.785    0.758    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_BA
    CLKIN_50M    0.801    0.774    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_BA    CLKIN_50M    0.799    0.772    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_BA    CLKIN_50M    0.801    0.774    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_CAS_N    CLKIN_50M    0.769    0.742    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_CS_N    CLKIN_50M    0.803    0.776    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ
    CLKIN_50M    0.806    0.779    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.768    0.741    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.796    0.769    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.796    0.769    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.762    0.735    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.759    0.732    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.796    0.769    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.806    0.779    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.783    0.756    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.763    0.736    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.789    0.762    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.779    0.752    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.766    0.739    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.782    0.755    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.769    0.742    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.756    0.729    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    0.776    0.749    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQM
    CLKIN_50M    0.793    0.766    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQM    CLKIN_50M    0.793    0.766    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQM    CLKIN_50M    0.768    0.741    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_RAS_N    CLKIN_50M    0.766    0.739    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_WE_N    CLKIN_50M    0.790    0.763    Rise    u1|altpll_component|auto_generated|pll1|clk
CORE_CLK    CLKIN_50M        0.579    Fall    u1|altpll_component|auto_generated|pll1|clk
SDRAM_CLK    CLKIN_50M    2.955        Rise    u1|altpll_component|auto_generated|pll1|clk
SDR_CLK    CLKIN_50M    3.390        Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_CLK    CLKIN_50M        2.878    Fall    u1|altpll_component|auto_generated|pll1|clk
SDR_CLK    CLKIN_50M        3.067    Fall    u1|altpll_component|auto_generated|pll1|clk