high-level become 2v!!

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originally posted by wbqyy@Dec 21 2005, 08:10 PM

hi: i met a very strange phenomenon!

i define a bidir port named daccontrol[1..0],then i write the direction register so that i could define it as a output port, then i output a "1" to daccontrol[1]

or daccontrol[0],in theory one of them should be3.3v ,another should be 0v,but both of them show 2v!

i have tried many times! when i write "1" to both daccontrol[1] and daccontrol[0],they show right! so is the data[0]!

thanks !! with my regards!

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There could be a number of things here: contention (something else attempting to drive that signal low), some large current sink attached to the I/O, etc.

Another possibility is that Altera FPGAs offer many choices for I/O standards for each pin; they can be programmed to operate at different voltages, using a combination of I/O bank power supply voltage, and settings inside Quartus II. To make sure this is not the problem, open Quartus II assignment editor and look for any assignments for I/O standard regarding the pin(s) in question. I believe that the &#39;LVTTL&#39; standard is the default, which on our dev boards wil provide 3.3V at logic &#39;1&#39;.

Again though, please do check for other hardware contention/current drain issues.

The IO direction may not working. So all the pins are Hi-Z input mode.

Make sure the access is "uncached".

Or try change the bidir port to a output only port, can help to identify the problem.