HI! I don't know instruction cycle

Is the memory SDRAM or onchip RAM or what?

If it's sdram, then the bus turnaround (or read and write addresses in different collumns, etc.) may be killing you.

Try using another register or so to do multiple LDW's and then multiple STW's.

Of course it would be nice if NiosII supported post or preincrement addressing. That would eliminate the ADDI's.

You can also try DMA as Sylvain suggests. I'm not sure if it does multiple reads and then multiple writes or not. It does have an internal fifo.

The key is to do two or more reads back to back and then writes.

Ken