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LKiên's avatar
LKiên
Icon for New Contributor rankNew Contributor
6 years ago

Hi everybody, I have a simple project using core Nios ii on qsys to control swicth led on board De2 -115 but when I complie , quartus report about "jdo" port in file nios2_gen_cpu.v .

Warning (12020): Port "jdo" on the entity instantiation of "the_led_nios2_gen2_0_cpu_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored.

I open file nios2_gen_cpu.v but it a asccii file . why it is a verilog file.

Thanks you very much

1 Reply

  • Ahmed_H_Intel1's avatar
    Ahmed_H_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Can you please share with me a sample screen shoot of the Qsys connections? and how you connected it in the TOP level file?

    Yes, the file is in Verilog to be compiled into the top-level for sure.

    Regards,