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Altera_Forum
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14 years ago

HELP:how to remove these timing critical warning

I get some critical warnings for timing,when I make the TSE project. I want to implement a 150MHz nios II system of TSE transciever, and I almost finish the hardware of nios II with the DE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Look for the top failing paths report in Timequest to determine where you need to add more pipelining.

A typical path that needs a pipeline bridge is the one between the Nios CPU masters (data and instruction) and the CPU's JTAG debug slave interface.

Going over 100MHz on a Nios II system on a Cyclone FPGA is possible, but requires some patience...