Help writing c code for NiosII_Stratix II_2s60

Hi,

I am stuck in one design for past 10 days. Working with Altera CYCLONE V FPGA board.

I am generating Trigger Signal for 500ns and 32-bit counter (Verilog), and at every (neck edge) positive edge of Trigger signal i need to collect and store that count data into reg (final_value).

Same thing, the counter is connected to FIFO and sends repeatedly bits to fill the FIFO that is connected to Nios.

Enable signal is given From PIO., and reading the counter data from NIOS

ISSUE: IN NIOS, same data printing continously for certain number of times.

Verilog Code

module Counter(
    input clk,                // 50Mhz
	 input enable,
    input reset,
    output reg[31:0] Final_value,
   output  reg trig
    );
    reg[31:0] counter_out;
    reg [7:0] temp=0;
    reg [31:0] counter_result;
    wire temp1;
    wire temp2; 
 
       
   always@(posedge clk)
   begin
    if(reset)
        begin
        trig<=0;
        temp<=0;
        counter_out<=0;
        end
    else if (enable==1'b1)
        begin
        counter_out<=counter_out+1;
        temp<=temp+1;
        if(temp==25)
            begin
            temp<=0;
            trig<=~trig;                    /// Generating COunter
            end
		  end
     end 
 
	 assign temp1=trig;
	 assign temp2=temp1&&clk;
	 always@(posedge temp2)
	 if(reset)
	    counter_result<=0;   
	  else 
	 begin
        counter_result<=counter_result+1;                    // Increaming the Counter
     end
  always@(posedge trig)                                         // Detecting Edge trig and storing into Final_value
  if(reset)
       Final_value<=0;  
   else 
  begin
       Final_value<=counter_result;                                         
  end
endmodule

Block Design

NIOS console