Forum Discussion
Altera_Forum
Honored Contributor
9 years agoSome issues i saw:
- reset unused (helps to have at least a default value when reading your register)
- read_n and write_n are low active (compare with 0 instead of 1, or use the high active signals)
- dataOut is pipelined for one cycle, make sure you have defined one read wait state in qsys/hw.tcl
- there is no address bus (qsys spans a only one single 32Bit word register map)
- you are writing to offset 1 (0x4 as byte offset), this is not your (single word) component