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Altera_Forum
Honored Contributor
15 years agoHelp me!!
(Quatus 9.1) Error (10170): Verilog HDL syntax error at multiplicador_3b.v(7) near text "begin"; expecting a description. module multiplicador_3b(P5, P4, P3, P2, P1, P0,A2, A1, A0 , B2, B1,...
Altera_Forum
Honored Contributor
15 years agoendmodule should be at the end of all...don't let your professor see that