Help in CRC custom instructions please.

Hello,

I think I have to stop looking into the custom instruction implementation for the arbitrary precision logic since the custom instructions are not really flexible. In my case if the custom instruction lasts for four clock cycles, I need to sample the new values for dataa and datab every clock cycle.

However, the definition of a multicycle custom instruction needs the operands dataa and datab to remain constant for that many number of clock cycles

for which the custom instruction runs. So in this case, I might have to wait for four clock cycles to get the result of first 32 bit + 32 bit addition which

does not serve the purpose of accelerating the speed of the instruction.

Another approach is to make the custom instruction hardware modules combinatorial and write to memory every time the sum and the carry and read from memory (the earlier carry) for the next set of 32 bit operands addition. This will also have the bottleneck of making the verilog hardware modules

talk to the memory for each and every clock cycle.

So I guess I have to look into some other mode of Hardware Acceleration.

I think I shall try to implement some hardware accelerators (IP cores) from the SOPC builder.

Please try to correct me if I am going in a wrong direction here. Any inputs are appreciated.

Thank you,

Akhil