Help in CRC custom instructions please.

Hello dsl,

Thank you for the reply! I think I am able to understand what you are saying here. I believe I have to come up with some sort of accumulator design

to store the intermediate values between the clocks.

I have a couple of questions here as well.

1) How to give the input ports c[4:0] some value when we call the corresponding macro from the custom instruction from the application C code in NIOS II IDE?

I designed a small verilog with c[4:0] and writerc ports in it. However after a build in NIOS II I looked into the 'system.h' file and see my custom instruction macro as:

# define ALT_CI_CUSTOM_COMPONENT_ADD_INST(n,A,B) __builtin_custom_inii(ALT_CI_CUSTOM_COMPONENT_ADD_INST_N+

(n&ALT_CI_CUSTOM_COMPONENT_ADD_INST_N_MASK),(A),(B))

I was wondering how the processor will act as the master and gives the signals like clk, clk_en, reset, start, writerc, c[4:0] etc to the verilog modules.

Is there some way in which I can set those values while running the code from NIOS II or even from the Quartus SOPC builder?

The custom instruction manual does not give any clue regarding these.

2) Is there a pin trace (like gtk wave utility) from NIOS II using which I can see the port values while running the code from NIOS II IDE. That will really help me a lot

to understand the signals.

I hope the questions are clear here.

Thanks in advance for your response.

Thank You,

Akhil Kalathungal