Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHello dsl,
Can you please explain to me a little bit more? I am still trying to understand the ways in which it can be implemented. I believe you intend me to use the 'Internal Register File Custom Instructions' than the 'External Interface Custom Instructions'. And by pulling the 'writerc' signal low, we can save the SUM output value to an internal register which can be addressed by c[4:0]. Please note that my full adder module can have a 'Carry Out' bit as well, which has to be propagated from one adder module to another. I was wondering how to store this? Since there is only one output port to a custom instruction (that is 'result') and that port is already used to store the SUM. The design I planned to use was something like this: Say if I need a 128 bit adder, then I will cascade 4 32 bit full adders. Please see the attached Full Adder Design text file which is attached. I am having a lot of questions here, like is it possible to cascade the four custom instruction blocks, or a better approach is to have a counter inside the custom design and do the instructions for four clock cycles, in each and every clock, read the cout bit and update the cout bit. In this case I guess I will have a space inside my accumulator where I can store intermediate carry out and result values. And raise the 'Done' signal after counting 4 clock cycles and doing the operations with it. Please advice me here, that will be a huge help. Thank You, Akhil