Honored Contributor
Honored ContributorProbably doesn't really matter at all.
Just start from a working version of one of the simple Altera configs. Unfortunately none of those seem to pass the timing constraints - so you can't (easily) tell if your logic is too slow! I remember having to drop the clock from 100MHz to 50MHz to get rid of some very strange errors! Although I wrote the custom instruction vhdl (the only vhdl I've actually written) and tested it on one of the cyclone III boards, it got built into out main image which runs on an arria II (I think) by the hw team. Writing custom instructions is probably a good way for reasonably experienced software engineers to get to understand VHDL. If there were better examples it would help!
