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Honored Contributor
13 years agoThe custom instruction has to contain all of it's own logic.
A multicycle custom instruction has clock and enable inputs, so can save values between cycles (but an OS context switch would have to save the internal state, or you have to disable context switches over instruction sequences that need the saved state.) It is worth realising that the nios cpu ALU works (effectively) by feeding the rA and rB register values into separate combinatorial logic for every opcode, and then uses a great big mux to select the required result. A simple combinational custom instruction would be one that replicates one of the standard ALU instructions (or even simpler, just returns one of the input registers). For multicycle something that returned one of the inputs the previous time the instruction was executed. But I don't remember seeing such examples! I didn't have any difficulty with the combinatorial ones - and I hadn't written any vhdl before (I have soldered TTL chips together). This is the vhdl of my crc16 instruction:-- crc16.vhd
-- Parrallel CRC generator for CRC16 (most hdlc).
-- Nios2 Custom instruction
-- Implements following C:
-- t1 = crc ^ data;
-- t2 = (t1 ^ t1 << 4) & 0xff;
-- return crc >> 8 ^ t2 << 8 ^ t2 << 3 ^ t2 >> 4;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity crc16 is
port (
data : in std_logic_vector(31 downto 0); -- 8 bit character value
crc_in : in std_logic_vector(31 downto 0); -- Old 16bit crc
crc_out : out std_logic_vector(31 downto 0) -- Updated crc value
);
end entity crc16;
architecture rtl of crc16 is
signal t1, t2: std_logic_vector(7 downto 0);
begin
t1 <= crc_in(7 downto 0) xor data(7 downto 0);
t2 <= t1 xor t1(3 downto 0) & B"0000";
crc_out <= X"0000" & (X"00" & crc_in(15 downto 8)) xor (t2 & X"00")
xor (B"00000" & t2 & B"000") xor (X"000" & t2(7 downto 4));
end architecture rtl;
The relevent part of crc16_hw.tcl is: set_interface_property crc_16 clockCycle 0
set_interface_property crc_16 operands 2
set_interface_property crc_16 ENABLED true
add_interface_port crc_16 data dataa Input 32
add_interface_port crc_16 crc_in datab Input 32
add_interface_port crc_16 crc_out result Output 32