Help in CRC custom instructions please.

Thanks a lot for the valid input. I was looking into the custom instruction pdf of the NIOS ii which is at the link:

altera.com/literature/ug/ug_nios2_custom_instruction.pdf

There I see External Interface Custom Instructions Figure 1–9. Custom Instructions Allow the Addition of an External Interface.

The page states:

"Custom instruction logic can perform various tasks such as storing intermediate results or reading memory to control the custom instruction operation. The conduit interface also provides a dedicated path for data to flow into or out of the processor. For example, custom instruction logic with an external interface can feed data directly from the processor’s register file to an external first-in first-out (FIFO) memory buffer."

So if we are able to interface a memory buffer with the custom instruction logic, we will be able to store the intermediate values.

Say we would like to add 1024 + 1024 bit data. Cannot we use the above concept to add 32 + 32 bits * 32 times and storing the intermediate results

in a memory buffer (of course the carry bit has to propagate) and later stitching all the bits together to form the final result?

Looks like the above External Interface can be implemented in multi-clock cycle (32) custom instruction method.

If my above assumption is correct, please read on.

Is it possible to come up with a custom instruction, like ADD1024 (looks like the normal ADD) which implements the above functionality.

If possible, what is the method to create a custom instruction? From an upper level the application programmer can use the built-in-macros.

However I guess the SOPC builder has to create the custom instruction from a lower level? If so, what is the process?

From where I can start?

Really appreciate for the response.

- Akhil