Hardware vs Software interupt

I haven't read that chapter of the handbook, but perhaps it is refering to software exceptions? (Illegal instruction exceptions, TRAP instructions, etc.)? These are processor-specific things, can generate a software exception. These will be documented in the processor documentation. They are, generally speaking, not generated by events external to the processor.

By contrast, hardware interrupts come from peripherals external to the CPU, whether the peripheral is implemented in the FPGA ot not. For example, if you have a slave peripheral, it could generate an interrupt by emitting an irq signal which is connected to Avalon along with the other slave signals. This signal is sent via Avalon (and how you connect that interrupt in SOPC Builder), to the various master peripherals connected to the slave. The behavior and response of each of these masters is dependent on the design of that master; for the Nios II CPU, external interrupts are another exception source (in addition to the software exceptions described above), and they are treated as described in the processor handbook. In addition to the low-level handling of an external interrupt by the CPU, there is typically some software involved that prioritizes incoming interrupts, adjusts the CPU's interrupt enable register bits, and vectors off to interrupt service routines as appropriate... this part is pretty common to how most CPUs operate.

There will be a quiz on Friday covering this lecture........