Gigabit Ethernet Interface (via Marvell 88E1111) with Cyclone IVE FPGA

Hi,

In IP core summary, it shows NIOSII Processor and Triple speed Ethernet with license type: OpenCorePlus and other components licence type: N/A.

With the DE2-115 board, Quartus II DVD is also delivered Which contain Megacore IP LIbrary. I think those required IP could be available in this DVD.

Is it true that the licence for this Megacore IP Library delivered with the board expires after 1 year??

Actually, I am using QuartusII 12.1 Web edition but not the one delivered with the board as it is older version (Quartus II v10.0).

Probably I have to switch to this older but Subscription edition Quartus to use the feature of IP library. Does this older version (Quartus II v10.0) also support Tripple speed ethernet?

or

Is it also possible to implement Gigabit Ethernet completely in Hardware? I mean to write the complete VHDL code for both the system and application running on it? I mean not using any software like C/C++.

Quartus 10 supports TSE.

Implementing the complete Ethernet protocol in VHDL is possible but will take time. Alternatively you can have a look at the Ethernet MAC available at Opencores, or buy the license for the TSE ($500 per year if I remember correctly).

Because people often want to use a NIOS along side the Ethernet, it sometimes makes sense to purchase the IPS-EMBEDDED bundle:

http://www.altera.com/devices/processor/nios2/ipsuite/ni2-ip-suite.html

As far as licensing terms go, every IP we have purchased has had perpetual use with 1 year of updates.

Regarding doing everything in HDL, see the UDP Offload example:

http://www.alterawiki.com/wiki/nios_ii_udp_offload_example

You can start with a scheme like that and then hardcode / trim down everything to get rid of the NIOS + software if you are working with a closed system (e.g. you just want a point-to-point link to broadcast/receive streaming data between two boards using Ethernet as the transport).

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e.g. you just want a point-to-point link to broadcast/receive streaming data between two boards using Ethernet as the transport.

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Yes, I just want a point-to-point link to broadcast/receive streaming data from FPGA board to another device (lets say PC at the beginning) using Ethernet as the transport and Speed should be like 500 Mbps at least.

I read the link you have provided, but how can I trim down NIOS and software part from it for my purpose?

Hi,

This means better is to buy IP cores.

Anyway, i would like to modify the tutorial but first I didn't understand completely the application program written in C.

I didn't understand which values are assigned to pointer *tse and how the address of pointer is incremented below?

// Triple-speed Ethernet MegaCore base address

volatile int *tse =(int *) 0x00102000;

// Initialize the MAC address

*(tse + 3) = 0x116E6001;

*(tse + 4) = 0x00000F02;

// Specify the addresses of the PHY devices to be accessed through MDIO interface

*(tse + 0x0F) = 0x10;

*tse + 0x10 = 0x11;

// Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback

*(tse + 0x94) = 0x4000;

// Write to register 16 of the PHY chip for Ethernet port 1 to enable automatic crossover for all modes

*(tse + 0xB0) = *(tse + 0xB0) | 0x0060;

// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk

*(tse + 0xB4) = *(tse + 0xB4) | 0x0082;

// Software reset the second PHY chip and wait

*(tse + 0xA0) = *(tse + 0xA0) | 0x8000;

while (*(tse + 0xA0) & 0x8000)

;

// Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding

*(tse + 2) = *(tse + 2) | 0x0000004B;

can anybody please clarify me?

Those are the TSE's configuration registers. You'll find a list in the datasheet here: http://www.altera.com/literature/ug/ug_ethernet.pdf

By the way this is a bad way of doing it. The TSE's base address and the register numbers are hard coded in the source code, which makes it difficult to read and maintain.

I'd recommend instead to include the <system.h> file, which should include a TSE_BASE (if your TSE component is called "tse" in your project) definition with the base address to use instead of the hard coded 0x00102000.

Then if you include the <triple_speed_ethernet_regs.h> file you will find a np_tse_mac structure that you can use to access all the configuration registers. Just replace the first line with something like

np_tse_mac *tse = (np_tse_mac*) TSE_BASE;

and then use tse->xxx to access the different registers.