Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi,
--- Quote Start --- On the 9th SCL's rising edge I get a half voltage level which is interpreted as a NAK by the i2cdetect utility. This curious case disappears if I configure the SCL as "output only". This brings me to think about my pins configuration: as the SCL and SDA lines are open drained, I configured them as such. --- Quote End --- Did you make the SCL and SDA 'hardware pins' open-drain ? It seems that a bus fighting occurs. The SDA line is used bidirectionally, your FPGA pin must be tri-state when the slave returns the ACK (= 0) signal. The open-drain pin is a simple method to achieve this. The SCL pin can be 'output only' if you don't have other I2C master except your FPGA. Kazu