Generating Hierarchical Systems in Qsys

All of the CPUs should be showing up assuming you are generating the top level system which contains the CPUs below it or within it.

There seems to be some confusion about what you need to generate. Think of this like verilog or VHDL, you compile a top level module and all the children are compiled too. The same goes for Qsys, if you generate the top level system then all of the children (and their children, and so on....) are generated as well.