Generating Hierarchical Systems in Qsys

hi

I did every thing in the right flow as you mentioned.

I design a hierarchical system in Qsys. In our design we have a "Top Level System" contains 3 subsystems, which each have one processor NiosII, JTAG, and "avalon memory map pipeline bridge". Cod memory of this processors define as "absolute" type, which is maped to a memory in the Top level system by "avalon memory map pipeline bridge ".

But I still have problems as below:

If we create a .sopcinfo file for a subsystem, and attempt to build a BSP based on that .sopcinfo file, when the BSP or application tries to refer to components in the top level, those references fail.

I found this solution for my problem:

"you must generate a .sopcinfo from

the top-level system, and base the BSP on this .sopcinfo file."

Unfortunately, I have only the .sopcinfo file of top-level system.(that means I do not have .sopcinfo file of subsystems!!!).

Please help me in this problem.

Thanks a lot.