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The maximum freqency will depend on other parts of the sopc system, and how full (or rather empty) the fpga is.
The maximum will also require correct timing definitions during synthesis - since internal registers probably need to be replicated (etc).
I don't believe anything in the fpga is 'dynamic' (ie needs clocks to hold its state), so the minimum speed ought to be 0Hz - however the JTAG (and any other external interface) may enforce a minumim clock speed.
Also, any external memory (SRAM) is usually run with a clock generated by PLL to be a few ns ahead of the nios clock - this won't work if you are dynamically changing the clock speed.
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Hi,thank you for your information. I used the PLL to generate several clocks and used the multiplexer to choose one of them to feed the clock of the Nios II processor at runtime. It seems that it works very well.I used bridges to gap the processor and memory(memory's clock doesn't change). I will not access any memory until the processor's clock is stable. It looks that it works very well..:confused:
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