FPGA to NIOS connection : counter value from FPGA print in NIOS

Yes both are running at 50MHz, but it takes more than a single clock cycle for the Nios processor to read the value from the counter, and then print it to wherever you are printing it to. That means the effective speed of the Nios processor is (much) lower. "Inserting a FIFO" wouldn't help with that - adding one would only slightly delay the inevitable data loss as it will rapidly fill up and overflow.

It doesn't matter whether it is a counter or a video source, you need some form of flow control to ensure that the Nios can read all samples. Alternatively do away with the processor completely and simply write an HDL block which takes a value and sends it over RS232.

However RS232 will probably not be fast enough for what you want to do. Even if you ran at 2MBaud which is probably on the highest end of what an RS232 transceiver could handle - i.e. 2MB of data per second - you could barely get 30FPS of 240x160 8-bit video through it. In practice you probably wont get anywhere near that either due to speed limitations of the RS232 or the fact that the software at the other end probably couldn't handle that amount of data continuously through its UART software.