FPGA design & user program in EPCS?

Hi Andrew,

> if I set the reset address to RAM or regular flash, wouldn't the CPU crash

> when it jumps there and finds garbage.

Yes ... if it finds garbage there. I keep a stable boot monitor in the epcs, but I put test code

and filesystem images in standard parallel flash. The boot monitor can program the flash

much (_MUCH_) faster than the flash programmer (via ethernet).

So for test and debug I just load a sof that has the reset address in the parallel flash

via JTAG since it's much more convenient. If things go belly up, I hit the hw reset and use the

image from the epcs -- I'm just plain lazy I suppose ;-)

> wouldn't loading the user program out of the EPCS necessitate a reset

> address set to the EPCS?

Normally, yes. But I may have misunderstood your original question. So, I think we might be

talking apples and oranges. You can have a reset address outside of the epcs then jump into

the epcs bootloader -- admittedly a hack -- and not necessarily a good practice ;-) -- although it

does work fine ... but this is all for test & debug ... not product.

Regards,

--Scott