Floating point pachage

These are the IEEE fixed point packages. They define types and functions that make using fixed point numbers easier in VHDL. There is a similar floating point ppackage, but I wouldnt recommend using it for synthesis.

signal A : ufxied(4 downto -3); --3 bits fractional
signal B : ufixed(4 downto -3);  -3 bits fractional
signal AtB : ufixed(9 downto -6);
signal ApB : ufixed(5 downto -3)
process(clk)
begin
  if rising_edge(clk) then
    AtB <= A * B;
    ApB <= A + B;
  end if;
end process;