Flash read causes two reads

Thank you all for your input.

As far as I understand, the Intel device on the Stratix III dev board is not byte accessible at all--there is no A0, so I don't understand how byte enables would play into this.

It does make sense to me however that the 32-bit Avalon slaves always do 32 bit reads and that's why two 16 bit reads would occur.

dsl, speaking of "Or maybe it is possible to map the flash memory at multiple addresses with different properties ..." I noticed that in the Stratix III example project, they mapped the one flash to two Avalon slaves connected to a single tristate bridge. My colleague and I could not figure out why they would do this, except if it's because there are byte accessible devices sharing the same address and data lines and some odd setup has to be done to make it work.