Flash programming for DE2-70

Hello hippo,

The reset vector on SOPC builder is set to "ext_flash" at 0x0. This is the name indicated in

http://www.nioswiki.com/mtd

is this name ok? or should I change it for 'cfi_flash' or 'cfi_flash_0' ?

should I disable the onchip-mem? But I guess there is no problem as long as the reset vector points to the ext_flash?

The addresses for my system are:

Below is my configuration for SOPC

ext_flash base=0x00000000 end=0x007fffff

epcs_controller base=0x00e05800 end=0x00e05fff

on the cpu SOPC:

reset vector offset 0x0 in ext_flash

I also checked the Data cache line size is set to 32 Bytes. I recall reading somewhere that this parameter should be set to 4 bytes, but don't know if this has got something to do with the problem. Besides, I was working on an Altera DE2, and now I'm working with a DE2-70, and 32 Bytes was set for the DE2_70_NET example. When running from SDRAM, there was no problem using 32-byte width.

my hardware selection

--- Please select which CPU you wish to build the kernel against:
(1) cpu - Class: altera_nios2 Type: f Version: 7.08
Selection: 1
--- Please select a device to execute kernel from:
(1) sdram_u2
        Class: altera_avalon_new_sdram_controller
        Size: 33554432 bytes
(2) onchip_mem
        Class: altera_avalon_onchip_memory2
        Size: 8192 bytes
(3) ssram
        Class: altera_avalon_cy7c1380_ssram
        Size: 2097152 bytes
(4) sdram_u1
        Class: altera_avalon_new_sdram_controller
        Size: 33554432 bytes
(5) epcs_controller
        Class: altera_avalon_epcs_flash_controller
        Size: 2048 bytes
(6) cfi_flash_0
        Class: altera_avalon_cfi_flash
        Size: 8388608 bytes
Selection: 6         

If I 1)add the default configuration, and then 2)the MTD support and flash tools, should I be able to see the default config booting from flash using the commands?

I didn't change anything from altera.c or nios2.h, I believe those are some of the files that require modification?

when I do

elf2flash --base=0x00000000 --end=0x007fffff --reset=0x0 --input=/home/pancho/nios2-linux/uClinux-dist/images/zImage --output=ext_flash.flash --boot=/opt/altera8.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec

is --reset the reset vector specified in the cpu?

and in

nios2-flash-programmer --base=0x0 ext_flash.flash

is --base the base address for the ext_flash?

Do I need to enable SPI and NAND flash as well? I am loading HW config into epcs and the OS to CFI flash.

also from

http://www.nioswiki.com/mtd

--- Quote Start ---

The CFI flash component should be named as "ext_flash", and the EPCS controller component should be named as "epcs_controller", otherwise you have to modify linux-2.6/arch/nios2/kernel/config.c .

The mtd partition map is located in linux-2.6/arch/nios2/kernel/config.c . You will need to edit the maps and buswidth for your boards.

The EPCS controller is exactly an Altera SPI interface plus some onchip memory. And the EPCS flash is exactly SPI flash, so we use the SPI driver to access the SPI flash.

--- Quote End ---

These are some of the questions that come to my mind now

EDIT:

I also found on another thread the following suggestions

there are few things you need to look at:

1. open sopc builder and check your cfi controller is placed on 0x01400000 and exception is not given on cfi (if reset vector is on flash, it is ok) my exception vector is pointing to ext_flash as well. at offset 0x20. where should it point to?changed it to sdram

2. you have selected correct size and timing parameters in cfi controller which matches your flash device on board apparently this is done modifying altera.c and nio2.h this i haven't figured out yet.4. make sure flash programmer's current instance is taking reference of same nios project you are working on (else you just delete all instances of flash programmer and re instance again by selecting your working project) suppose this refers to cleaning the project and then make vendor_hwselect. if that's the case, done

5. check system library properties of nios ii project and make sure read/write memory, stake memory, heap memory are not falling into flash device. keep it in volatile device like sdram or ssram or onchip ram. no idea

Thank you very much.

Francisco