Honored Contributor
Honored Contributor> With u-boot on the \f core, it seems the dcache is not invalidated for
> a flash erase. u-boot is normally run with data cache disabled. Unfortunately, Nios-II does not provide a mechanism to disable the data cache (as many other processors do). Regardless, commands that affect cache coherency are expected to invalidate/flush the data cache as appropriate if the data cache is enabled ... so you should invalidate the appropriate memory regions in your flash_erase() and write_buff() routines. > 'md' does not bypass dcache, and maybe that is the way it should be, Correct. > so what is the proper way to handle this? If flash_erase() and write_buff() do not invalidate the affected memory regions, you can just use bit-31 bypass when specifying the address to the 'md' command. > Does cache_bypass macro just bypass or also update cache? It simply sets bit 31 of the address ... nothing more. The readx/writex macros (i.e. readb/writeb, readw/writew, etc) should be used when possible rather than CACHE_BYPASS. Regards, --Scott BTW: readx/writex are defined in include/asm-nios2/io.h.
