Flash programmer via ethernet

I am sticking with Q4.2 and NiosII1.01 until the dust clears.

SOPC says my reset address is in flash at 0x0 with offset 0x0.

The ptf agrees with this.

CPU_RESET_ADDRESS is 0x0,

reset_slave = "flash/s1";

reset_offset = "0x00000000";

The board is working HW and has displayed no flakeyness while running, but POR is always special.

I have created a stripped down project that includes the fs2 module which should allow me to step thru the flashed start.S.

This required moving from the e core to the s core so now I have a cache to think about. I am hoping I will see an incorrect

jump early in the code to explain this behavior. If the bug only occurs for a real power cycle and not a soft reset, I wont see it in the

debugger and will instead have to probe the buses directly. I don't have debug headers for these buses - any signaltap gurus out there?

I'll have to make sure to disable cache so all cycles are visible.

I'll swap the code locations as you suggest before I dive in.