Flash made me Crazy for several days.

You need to read the rest of the Nios II Flash Programmer User Guide, specifically the part about making a target board project at the end.

Basically, the flash programmer needs a .sof file that it will download to the Altera to act as a relay between the JTAG and the flash. There's a process, documented in the guide, to create the project for that relay. After creating the project, you add pins for the flash and any other signals (chip enables, for example), assign the pin numbers, and build the project. When you're done, you have a target board project. By putting its directory in your real project's directory, that target board is listed in the SOPC Builder. Select it, regenerate, and then the flash programmer will know what to do.

This really needs to be an FAQ. Lots of people miss the target board stuff in the Flash Programmer guide.

The target board stuff was deprecated as of 5.1. The target "board" design is no longer needed for successful flash programming. The current editions of the manual clearly state this fact.

Tommy, you do need to spend some more time reading the flash user's guide, but, it probably also makes sense to try the '--debug' option on the nios2-flash-programmer, via CLI. Following is a sample of what you should be seeing:

$ nios2-flash-programmer -c 1 --debug --base=0x0
Using cable "Nios II Evaluation Board ", device 1, instance 0x00
Resetting and pausing target processor: OK
Found CFI table in 16 bit mode
Raw CFI query table read from device:
   0: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
  10: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
  20: 51 00 52 00 59 00 02 00  00 00 40 00 00 00 00 00  Q.R.Y.....@.....
  30: 00 00 00 00 00 00 27 00  36 00 00 00 00 00 07 00  ......'.6.......
  40: 07 00 0A 00 00 00 01 00  05 00 04 00 00 00 17 00  ................
CFI query table read from device:
  10: 51 52 59 02 00 40 00 00  00 00 00 27 36 00 00 07  QRY..@.....'6...
  20: 07 0A 00 01 05 04 00 17  02 00 05 00 01 7F 00 00  ................
  30: 01 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
CFI extended table read from device:
   0: 50 52 49 31 33 08 02 01  01 04 00 00 01 B5 C5 05  PRI13...........
  10: 01 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
Read autoselect code 0001-227E (in 16 bit mode)
No CFI override data for 
Device size is 8MByte
Erase regions are:
  offset        0: 128 x 64K
Device supports AMD style programming algorithm
Multi-byte programming with 32 byte buffer
Sector erase timeout is 16s
Word program timeout is 256us
Buffer program timeout is 4ms
Leaving target processor paused

You will, obviously, get a different message... The output should help you to decide what the issue is...

Best Regards,

- slacker

Thanks,Mike and slacker.

I have tried to make description file for my taget board,I will do it this several days.But there is some problem.My PCB is made by protel,however the description file needs "wirelist" formate.

That description consist of:

Intro Tab

Netlist Tab <----------I don&#39;t have this wirelist formate file

Flash Memor Tab <-----------Can I only make configure of this,Because The SOPC can&#39;t get information for wirelist netlist.

Net Tab

Devices Tab

Groups Tab

Pass Throughs Tab

Files Tab

--- Quote Start ---

originally posted by tommycp@Oct 16 2006, 05:36 PM

thanks,mike and slacker.

i have tried to make description file for my taget board,i will do it this several days.but there is some problem.my pcb is made by protel,however the description file needs "wirelist" formate.

that description consist of:

intro tab

netlist tab <----------i don&#39;t have this wirelist formate file

flash memor tab <-----------can i only make configure of this,because the sopc can&#39;t get information for wirelist netlist.

net tab

devices tab

groups tab

pass throughs tab

files tab

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18720)

--- quote end ---

--- Quote End ---

Have you tried the "flash flow" mentioned on page 7-8 of the QII handbook? I think it should apply to 5.1, though it&#39;s probably written for 6.0.

Best of luck!

- slacker

slacker

And I find that there is some document,saying that:description without netlist can&#39;t work (just flash flows,is "flash flow"means justs configure flash,let alone other like:Net TabDevices TabGroups TabPass Throughs Tab Files Tab),unless modify class.ptf,which is generated by description editor.

Could anyone kow how to modify or read class.ptf

----------------------------------------------

document I found on net:

Flash Programmer

Flash only flow failure in IDE—Updated December 19, 2005

The Flash only flow of the Board Description Editor is used to run the Nios II Flash Programmer

on a custom board in IDE mode. When the Board Description Editor is run in the Flash Flow only,

wherein no board netlist (wirelist) is provided, the resulting PTF file is missing some entries

which are required for successful system generation in SOPC Builder. A subsequent attempt to

generate in SOPC Builder will issue the following error:

C:/altera/quartus51/sopc_builder/bin/europa/e_project.pm 310 CALLED (e_project::device_family)

WHERE <=== &#39;expected exactly one argument&#39; OCCURRED on

C:/altera/quartus51/sopc_builder/bin/europa/e_project.pm 1313

Workaround: The workaround is to use the Flash Programmer via command line or hand-edit the board

description PTF file as described below after running the Board Description Editor.

1. Run through the Flash Flow of the Board Description Editor as instructed in the Board

Description Editor (PDF) chapter of the SOPC Builder Handbook.

2. Close SOPC Builder

3. In a text editor, open the .ptf file created by the Board Description Editor.

4. In the CLASS/BOARD_DEFAULTS section of the .ptf file, add the following entries.

o device_family = "<device family>"; suitable values for <device family> are CYCLONE, CYCLONEII,

STRATIX, STRATIXII, etc.

o For each CFI or EPCS flash entered in the board description, create a REFDES section with an

arbitrary base address, such as just "0".

o Workaround_example.txt shows an example of the edits.

5. Save and close the .ptf file after making the edits.

6. Re-open the system in SOPC Builder, select the newly created board description in the "Target"

section, and then click Generate.

==========================================================

CLASS my_1c20_no_wirelist_board

{

BOARD_DEFAULTS

{

class = "my_1c20_no_wirelist_board";

class_version = "1.0";

altera_avalon_epcs_flash_controller

{

reference_designators = "U59";

}

altera_avalon_cfi_flash

{

reference_designators = "U5";

}

reference_designators = "U59,U5";

initial_system_file = "";

# >> Add these lines or equivalent <<

>> device_family = "CYCLONE";

>> REFDES U5

>> {

>> base = "0";

>> }

>> REFDES U59

>> {

>> base = "0";

>> }

# >> End add lines <<

CONFIGURATION user

{

==========================================================

----------------------------------------------

thanks

--Tommy