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Altera_Forum
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19 years ago

FIFOed Avalon Uart

I have posted the FIFOed avalon UART in the Hardware Projects area. It is the standard UART that comes with Nios but it has additional features such as FIFOs and hardware CTS fifoed avalon uar...
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Altera_Forum
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15 years ago

Hi

Possible bug in FIFOed uart9.3

I am routing 9 Uarts to 1 all running at 460800baud. I had to implement RTS for each in the FPGA using the exported fifo registers - would be a nice standard feature:). All worked great in buffering the rx-ed data, but I started loosing rx data as soon as I started sending data back on the uarts.

It turned out that I lost all the data in the rx buffer (on the drivers side - not fifo) due to a rx interupt that were generated as soon as I tx any data when the rx buffer is full (rx buffer wrapped to start). I have for now solved the problem by clearing the rx irq when the rx buffer is full without reading the reg. Not nice but it is working for now

Another possible bug is in the UART status reg (fifoed_avalon_uart_reg.h) is the position of the last two registers, FIFOED_AVALON_UART_STATUS_RX_TH_MSK (13) and FIFOED_AVALON_UART_STATUS_GAP_MSK (14). In the VHDL code they are swapped when the are passed to the status_reg.

I am using NIOS/Quartus ver 10 on Win7 64bit PC so the IRQ buffer problem might be as a result of this.

Thanks for a great UART component!

Herman