FIFOed Avalon Uart

Hi again,

I've just tried to use this with version 8.1 and have come across a minor problem, hinted at in the documentation, which is that it can't get the right clock in the SOPC GUI, but I fixed that by editting the .tcl file to hard code the clock to 100MHz (ok for me, but not for general use!).

I've just tried to build my project (VHDL) and it complained that the USEDW was the wrong size - should be 4 but was 9 bits - on the RX fifo. I created the component with 512 bytes of FIFO, so 9 bits is correct, but the component declaration at the head of the VHDL file hard sets the usedw width to (in this case) 3 downto 0.

Just spotted the gotcha in me fixing it by setting it to 8 downto 0 which is that the TX fifo uses 16 bytes, and so is 3 downto 0, so that's now complained.

So I've changed that to use lpm_width generic, but that's now complained elsewhere. It would appear that lpm_width is set to 8 on my TX fifo, despite only having 16 bytes.....

Is this all because I'm using 8.1, not 9.0?

Cheers,

Simon