Honored Contributor
Honored ContributorIf you memory is 8 bits wide, then you need to have an Avalon slave that is also 8 bits wide. The SOPC builder then includes a 'bus width adapter' than generates four 8bit slave cycles for each 32bit master cycle.
It is possible that, to avoid confusion, the tri-state bridge address lines are (usually) defined so that An is address 2^n - which would mean that A0 and A1 wouldn't be connected for a 32bit memory chip. For an 8bit memory chip A0 and A1 would be generated by the bus width adapter. For SRAM the ordering of the address lines doesn't matter - neither does that of the data lines (nor the data polarity). So they might be switched around to aid the board tracking.
