External SSRAM reading/writing problem

Hello,

There are still a couple of things that I don't understand. And I'm using some documents to find out the answers. First, Nios Development Board - Cyclone II Edition Reference Manual and Nios II development board schematic. What confuses me is that address lines of ssram are connected like A0 to ssram_a0, A1 to ssram_a1..., but lines ssram_a6 and ssram_a7 are connected to A19 and A20 and they are used for memory extension. Why aren't the lines ssram_a19 and ssram_a20 used for the extension? How do I then address the memory if two bits are excluded in the middle of the address?

This memory has byte addressing but I would like to use it just to write 32-bit data. So SOPC Builder User Guide suggest that two Avalon-MM Address Lines tri_state_bridge_address[0] and tri_state_bridge_address[1] should be unconnected. How will that affect the program code? Do I need to multiply each address by 4 to perform 2-bit left shifting?

I'm sorry if I'm not clear enough, but if necessary I'll try to explain better.

Nikola