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Altera_Forum
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14 years ago

Ethernet roundtrip time with NicheStack & Nios-II

Hi, We are using TSE IP with NichStack, MicroC OS-II on Nios-II. FPGA is running a simple UDP host which echoes all packets it gets from client. The client is a PC running real-time OS and con...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Yes, the difference is between two FPGA designs and same PC running the RTOS (same binary on PC). So the PHY/board is capable of gigabit link, but somehow can not establish with my design.

Good points for clk and reset signals on PHY - will look into it.

I am not manipulating MDIO at all, but that raises a good point: Can I deliberately tweak MDIO to go for gigabit, just in case? Is there a HAL API for this, if we know TSE's parameters from system.h?

-swguy