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Altera_Forum
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14 years ago

Ethernet roundtrip time with NicheStack & Nios-II

Hi, We are using TSE IP with NichStack, MicroC OS-II on Nios-II. FPGA is running a simple UDP host which echoes all packets it gets from client. The client is a PC running real-time OS and con...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I have provided static IP addr in one of the .h files. Will also try hardcoding in the get_ip_addr() call.

I am using the ref design "Nios-II Ethernet Acceleration" on the Nios-II eval, Stratix-II edition.

The ref. document for the Marvell 10/100/1000 PHY daughter card (santa cruz connector) says there is some layout issue, which causes the PHY and the DDR clks tied together. PHY clk is derived from SOPC PLL @ 125 MHz and the document says DDR controller must be disabled if you want to run the Ethernet due to this clk issue. It did not make sense to me as the ref design uses the DDR, and the pre-canned binaries seem to work.

Has anyone dealt with this issue?

Also trying to use the C2H for checksum. C2H documentation is old and 10.1 sp2 EDS does not have C2H - must use legacy EDS I think. Would C2H for checksum be better choice than custom instruction?

thanks,

-swguy