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Altera_Forum
Honored Contributor
16 years agoHi,
--- Quote Start --- I haven't modified anything to do with that. I'm not sure what you are suggesting -- putting the exception address somewhere other than 0x20? (which on this system is in DDR SDRAM) --- Quote End --- Of course, this depends on the MACRO# if defined(CPU_EXCEPT_ADDRESS_ASM) && (CPU_EXCEPT_ADDRESS_ASM != (LINUX_SDRAM_START + 0x20))
. If you select the location of exception address in SSRAM with SOPC builder, those scripts automatically set the new address of SSRAM to CPU_EXCEPT_ADDRESS_ASM. So the exception handler is copied to SSRAM. And this is not controlled by linker scripts. If you select the location in DDR SDRAM, it's OK, no problem. --- Quote Start --- (What do those t's and T's mean?) --- Quote End --- Those are 'Symbol Types'. 'T' means that this symbol belongs to 'text' segment and is global. Kazu