Honored Contributor
Honored ContributorHi Cris,
Sorry I didn't make it clear. What I mean is after the Ethernet UDP packet(char data[1400]) is received in SSS, how should I offload these data to the FPGA so that my Verilog code can do further process for these data? (for instance, my verilog code has an input input [7:0] eth_data how will this input get the data[1400] received in Nios?) I used to use 9bit PIO and IOWR to transmit these data, but the data rate and stability seems not satisfying. Please give me some idea! Thank! --- Quote Start --- hi mickey I'm not sure I understand your request. Do you want to increase the 15Mbps figure or are you asking a way to transfer Ethernet UDP data to and from another fpga device? If it's the second one, please explain better what you need. --- Quote End ---
