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Honored Contributor
Honored ContributorError while simulating nios ii with custom component
Hello all, i want to simulate a Qsys system which contains nios ii and a custom peripheral. I created the testbench system in Verilog (Simple, BFMs for clocks and resets) and launch modelsim throu...
Altera_ForumHonored Contributor
Honored ContributorHello again,
i finally made had the program run (the first command printf("Hello world\n"); seeme to cause the problem...). But i come across a different problem: among the 3 registers' accesses (IOWR) only the last one is "saved". It acts as if the prior ones are set to '0'... Isn't it weird taking into account that my design works perfectly in hardware?? Thank you.
